When a microprocessor and memory such as a DRAM operate together, they must be able to communicate with each other in order that data are properly written into and read from the memory. Normally, however, the microprocessor and the memory do not speak the same language. The microprocessor delivers a particular set of signals in conjunction with transferring data to or from storage, but the memory requires a different set of signals in order to play its complementary role in the data storage/retrieval process. In the case of a DRAM, the refresh cycle may also require communication with the microprocessor. Therefore, an interface or controller is required, to receive the signals from the microprocessor and convert them into signals that can be understood by the memory.
Interface circuits which use common microprocessor control signals to control a DRAM fall into essentially two categories: those which rely on delay lines, and those which rely on clocked state machines. In the delay line approach, a particular strobe signal is used to initiate an external delay line device. The delay line has a number of taps which provide rising or falling edge signals at preselected intervals. The problem with the older delay lines is that many are bulky and inaccurate. The newer, solid state delay lines are more accurate, but they are quite expensive. In general, many computer designers are reluctant to use delay line circuits.
In the clocked state machine approach, flip-flops are arranged to form state machines which generate the required timing. Since a particular flip-flop can be either rising-edge triggered or falling-edge triggered (but not both), two sets of flip-flops are required to trigger events on both edges of a single clock pulse. This prevents the design from being suitable for implementation on a PLD (programmable logic device).
Alternatively, a second "2X" clock is added to provide a clock pulse at twice the frequency of the internal microprocessor clock. This allows all rising-edge triggered flip-flops to be used, and permits the design to be implemented in a PLD. However, where no internal 2X clock is available, an external 2X clock must be provided. This adds to the expense of the interface. Moreover, in high speed systems (for example, those operating at 16 MHz) there is the problem of determining and minimizing the skew between a 32 MHz state machine clock and the 16 MHz microprocessor clock. If the skew is indeterminate or very long, it is difficult to keep the 2X clock and the microprocessor's clock tightly synchronized. A further problem arises from the fact that some microprocessors have a clock scaling function which saves power by allowing the central processor unit to slow down the clock during periods of inactivity. Most clock state machines are unable to anticipate such random changes in the timing of the CPU clock.
In accordance with this invention, a DRAM control circuit is provided which avoids the need for a 2X clock or two sets of flip-flops, one rising-edge triggered and the other falling-edge triggered.